The present disclosure generally relates to semiconductor device manufacturing and, more particularly, to the cleaning and removal of residues and/or contaminants formed on the semiconductor device during manufacture.
The integrated circuit manufacturing process can generally be divided into front end of line (FEOL) and back end of line (BEOL) processing. The FEOL processes are focused on fabrication of the different devices that make up the integrated circuit, whereas BEOL processes are focused on forming metal interconnects between the different devices of the integrated circuit. In the FEOL processes, shallow trench isolation structures and gate or memory stacks are typically formed. These structures are fragile due to their increasingly small dimensions and the types of materials used to form the structures. BEOL processes may also have fragile structures such as dual damascene etched openings in low k dielectric materials or polysilicon interconnect lines. Often BEOL processing includes one or more chemical mechanical planarization (CMP) process steps, which are inherently very dirty processes.
The number of photoresist cleaning or stripping steps employed in the semiconductor manufacturing process has grown greatly in the last few years. The increasing number of ion implantation steps has contributed greatly to this increase. Current high current or high energy implant operations are the most demanding in that they require a high degree of wafer cleanliness to be obtained while minimizing or eliminating photoresist popping, surface residues, and metal contamination while requiring substantially no substrate/junction loss or oxide loss. Likewise, the semiconductor manufacturing process will typically include one or more CMP processes that typically employ abrasive slurries and rotating pads/brushes to effect surface planarization. Defect minimization during semiconductor manufacture is of great interest to the overall success as devices are scaled to smaller dimensions. For example, ceria nanoparticles are often used as the CMP slurry for next generation technology nodes because defect levels are at or below the more traditional silica-abrasive slurries and also because very low concentrations can effectively be used, which translates to lower levels of contamination. However, the semiconductor devices as well as the CMP pads/brushes are often contaminated with particles of ceria that require removal for successful and efficient device manufacture.
Because of the extraordinarily high levels of cleanliness that are generally required during the fabrication of semiconductor substrates, multiple cleaning steps are typically required to remove impurities from the surfaces of the substrates before subsequent processing. A typical surface preparation procedure may include etch, clean, rinse and dry steps. During a typical cleaning step, the substrates may be exposed to a cleaning solution that can include mixtures of hydrogen peroxide and ammonium hydroxide, and/or hydrochloric acid, and/or sulfuric acid, and/or hydrofluoric acid with a surfactant. These solutions are commonly referred by those in the art to as SC1, SC2, HPM, APM and IMEC cleaning solutions. After cleaning, the substrates are rinsed using ultra-pure water and then dried using one of several known drying processes. In some instances, the cleaning solutions may be in combination with acoustical cleaning methods, e.g., ultrasonics, megasonics, and the like.
In various advanced development processes required for semiconductor device manufacture, either rare earth metals or transition metals are required to be selectively removed in the presence of very similar metallurgy. In addition, reactive ions etch (RIE) or CMP processes may leave modified residues related to these rare earth or transition metallurgy. In FEOL processes, the typical cleaning chemistries are not selective enough to differentiate between some of these residues that must be removed or metals and the metals required to remain. For example, SC1 is commonly used to remove FEOL residue, but is also known to attack TiN surfaces. TiN is used as a component of some metal gate structures and any loss of TiN in these metal gate structures can result in an undesirable decrease or change in device performance.
Accordingly, it would be desirable to have a process and chemistry that is capable of removing undesired residue without producing a undesired decrease or change in device performance.